Reg

Address

Reg

Name

Write/

Read

B7

B6

B5

B4

B3

B2

B1

B0

   

0x00

R0

W

           

0x01

R1

W

           

0x02

R2

W

 

FILT_Q

   

LT_ATT (0-7)

   

0x03

R3

W

           

0x04

R4

W

           

0x05

R5

W/R

PWD_LT

cable_in

PWD_LNA1

LNAGAIN_MODE

LNA_GAIN[3:0]

   

0x06

R6

W/R

PWD_PDET1

PWD_PDET2(3?)

FILT_3DB

1 V6Mhz

Cable2

PW_LNA[2:0]

Verify PWD_x

  

0x07

R7

W/R

IMG_R

PWD_MIX

PW0_MIX

MIXGAIN_MODE

MIX_GAIN[3:0]

   

0x08

R8

W/R

PWD_AMP

PW0_AMP

Q/I

IMR_G[4:0]

 

Image reject – to verify

 

0x09

R9

W/R

PWD_IFFILT

PW1_IFFILT

Q/I

IMR_P[4:0]

pwd cuts signal

 

0x0A

R10

W/R

PWD_FILT

PW_FILT

Low Q

FILT_CODE[3:0]

pwd cuts signal

Low-Q: should give less sharp filter edges

 

0x0B

R11

W/R

1.7MHz BW

FILT_BW[1:0]

CAL_TRIG

HPF[3:0]

 

Cal: needs testing

 

0x0C

R12

W/R

1 ADC enable=0

PWD_VGA

pw0_vga

VGA_MODE

VGA_CODE[3:0]

   

0x0D

R13

W/R

LNAVTH_H[3:0]

LNAVTH_L[3:0]

ok

  

0x0E

R14

W/R

MIXVTH_H[3:0]

MIXVTH_L[3:0]

ok

  

0x0F

R15

W/R

FLT_EXT_WIDEST

ldo5vh

pwd_ldo_5v

CLK_OUT_ENB

1 ring clk=0

CALI_CLK

CLK_AGC_ENB

GPIO_enable

GPIO: There is only one pin, status (input) should be within R1-R4

  

0x10

R16

W/R

SEL_DIV[2:0]

REF_DIV2

xtal_drive low=1

agc_clk_s2

CAPX[1:0]

AGC_CLK: Test with AGC enabled on pulsed RF signal, capx is filtering unknown

  

0x11

R17

W/R

PW_LDO_A[1:0]

CP_CUR

pwd_divider

1 1 biasHF

   

0x12

R18

W/R

VCO_CURRENT

DIS_DITHER

PW_SDM

cp_offset

Cp_0406

VCO current: try VCO range with different currents

  

0x13

R19

W/R

PLL auto_tune clk 0=on

band force 1=on

VCO band

   

0x14

R20

W/R

S_I2C[1:0]

N_I2C[5:0]

N

Vital part of tuning

 

0x15

R21

W/R

SDM_IN[8:1]

Frac

 

0x16

R22

W/R

SDM_IN[16:9]

 

0x17

R23

W/R

PW_LDO_D[1:0]

DIV_BUF_CURR

OPEN_D

1 0 pw_IQ

0 PWD_IQ

Open-D: GPIO related? External control of something NOT in RTL-SDR sticks aka filter switch?

  

0x18

R24

W/R

0 pw_ringout

1 ring_cp

- ring_se23

- ring power=1

N_RING

Calibration only

  

0x19

R25

W/R

PWD_RFFILT

ring_cp_current

POLYFIL_CUR

SW_AGC

1 1 ring_pw

ring_seldiv

   

0x1A

R26

W/R

RFMUX[1:0]

AGC_CLK

PLL_AUTO_CLK[1:0]

RFFILT{1:0]

PLL_AUTO_CLK: test by time to lock on frequency change

  

0x1B

R27

W/R

TF_NCH[3:0]

TF_LP[3:0]

Needs testing

  

0x1C

R28

W/R

PDET3_GAIN[3:0] – vga

lna_top_p1

DISHARGE_MODE

mixer src 0=rf 1=ring

VCO_Out

 

PDET#_Gain: needs signal generator to check amplification, R1 / R3 for status

Seems broken

 

0x1D

R29

W/R

1 1 DETECT_BW

PDET1_GAIN[2:0] LNA

PDET2_GAIN[2:0] mixer

  

0x1E

R30

W/R

sw pdect 1=det3

FILTER_EXT

ext_enable_point

PDET_CLK[4:0]

Bit 7: imr meassurement, also mixer AGC seems to act on VGA level instead of mixer level

  

0x1F

R31

W/R

LT_ATT (3db)

CLK-unknown

0

0

0

0

ring_att

Bit 6: meassure clkout on a actual dongle, 5-2: unknown function (but active according to map)

  

0x20

R32

-

           
              

/* adc=on, vga code mode, gain = 26.5dB */

rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);

  
     
     
   

known to work

          
   

can’t be supported due to chip limits (as far as we know)

          
   

No effect or wrong effect

          
   

Hard/can’t be confirmed

          
   

Not primary priority but can make stuff interesting

          
   

unknown

          
   

Preliminary testing – does something expected – missing final test

          
   

Meassured change, unknown effect

          
              
              
              
   

GPIO: Pin1 on the tuner (NC – not connected or no connect) may be the GPIO pin

          

Reg

Address

Reg

Name

Write/

Read

B7

B6

B5

B4

B3

B2

B1

B0

  

0x00

R0

R

1

0

0

1

0

1

1

0

  

0x01

R1

R

-

-

ADC OUTPUT

  

0x02

R2

R

0 (1) – GPIO candidate

LOCK (1=lock)

VCO_BAND

 

LNA

0x03

R3

R

MIXER GAIN

LNA GAIN

 

PLL

0x04

R4

R

-

-

VCO_FINE_TUNE

CAL_CODE

 

Cal

0x05

R5

W/R

PWD_LT

cable_in

PWD_LNA1

LNA_GAIN_MODE

LNA_GAIN[3:0]

 

Filter

0x06

R6

W/R

PWD_PDET1

PWD_PDET2

FILT_3DB

1 V6Mhz

Cable2

PW_LNA[2:0]

 

AGC

0x07

R7

W/R

IMG_R

PWD_MIX

PW0_MIX

MIXGAIN_MODE

MIX_GAIN[3:0]

  

0x08

R8

W/R

PWD_AMP

PW0_AMP

IMR_G[5:0]

  

0x09

R9

W/R

PWD_IFFILT

PW1_IFFILT

IMR_P[5:0]

 

Power

0x0A

R10

W/R

PWD_FILT

PW_FILT

Low Q

FILT_CODE[3:0]

  

0x0B

R11

W/R

1.7MHz BW

FILT_BW[1:0]

CAL_TRIG

HPF[3:0]

  

0x0C

R12

W/R

1 ADC enable=0

PWD_VGA

pw0_vga

VGA_MODE

VGA_CODE[3:0]

  

0x0D

R13

W/R

LNAVTH_H[3:0]

LNAVTH_L[3:0]

  

0x0E

R14

W/R

MIXVTH_H[3:0]

MIXVTH_L[3:0]

  

0x0F

R15

W/R

FLT_EXT_WIDEST

ldo5vh

pwd_ldo_5v

CLK_OUT_ENB

1 ring clk=0

CALI_CLK

CLK_AGC_ENB

GPIO_enable

  

0x10

R16

W/R

SEL_DIV[2:0]

REF_DIV2

xtal_drive low=1

agc_clk_s2

CAPX[1:0]

  

0x11

R17

W/R

PW_LDO_A[1:0]

CP_CUR

pwd_divider

1 1 biasHF

  

0x12

R18

W/R

VCO_CURRENT

DIS_DITHER

PW_SDM

cp_offset

Cp_0406

  

0x13

R19

W/R

PLL auto_tune clk 0=on

band force 1=on

VCO band

  

0x14

R20

W/R

S_I2C[1:0]

N_I2C[5:0]

  

0x15

R21

W/R

SDM_IN[8:1]

  

0x16

R22

W/R

SDM_IN[16:9]

  

0x17

R23

W/R

PW_LDO_D[1:0]

DIV_BUF_CURR

OPEN_D

1 0 pw_IQ

0 PWD_IQ

  

0x18

R24

W/R

0 pw_ringout

1 ring_cp

- ring_se23

- ring power=1

N_RING

  

0x19

R25

W/R

PWD_RFFILT

ring_cp_current

POLYFIL_CUR

SW_AGC

1 1 ring_pw

ring_seldiv

  

0x1A

R26

W/R

RFMUX[1:0]

AGC_CLK

PLL_AUTO_CLK[1:0]

RFFILT{1:0]

  

0x1B

R27

W/R

TF_NCH[3:0]

TF_LP[3:0]

  

0x1C

R28

W/R

PDET3_GAIN[3:0] – vga

lna_top_p1

DISHARGE_MODE

mixer src 0=rf 1=ring

VCO_Out

  

0x1D

R29

W/R

1 1 DETECT_BW

PDET1_GAIN[2:0] LNA

PDET2_GAIN[2:0] mixer

  

0x1E

R30

W/R

sw pdect 1=det3

FILTER_EXT

ext_enable_point

PDET_CLK[4:0]

  

0x1F

R31

W/R

LT_ATT

1(pwd_xtal?)

0

0

0

0

ring_att

  

Reg

Address

Reg

Name

Write/

Read

B7

B6

B5

B4

B3

B2

B1

B0

  

0x00

R0

R

1

0

0

1

0

1

1

0

  

0x01

R1

R

-

-

ADC OUTPUT

 

On=0

0x02

R2

R

autotune?

LOCK (1=lock)

VCO_BAND

  

0x03

R3

R

MIXER GAIN

LNA GAIN

 

On=1

0x04

R4

R

-

-

VCO_FINE_TUNE

CAL_CODE

  

0x05

R5

W/R

PWD_LT

cable_in

PWD_LNA1

LNA_GAIN_MODE

LNA_GAIN[3:0]

 

On=Auto/external

0x06

R6

W/R

PWD_PDET1

PWD_PDET2

FILT_3DB

1 V6Mhz

Cable2

PW_LNA[2:0]

  

0x07

R7

W/R

IMG_R

PWD_MIX

PW0_MIX

MIXGAIN_MODE

MIX_GAIN[3:0]

  

0x08

R8

W/R

PWD_AMP

PW0_AMP

IMR_G[5:0]

  

0x09

R9

W/R

PWD_IFFILT

PW1_IFFILT

IMR_P[5:0]

  

0x0A

R10

W/R

PWD_FILT

PW_FILT

Low Q

FILT_CODE[3:0]

  

0x0B

R11

W/R

1.7MHz BW

FILT_BW[1:0]

CAL_TRIG

HPF[3:0]

  

0x0C

R12

W/R

1 ADC enable=0

PWD_VGA

pw0_vga

VGA_MODE

VGA_CODE[3:0]

  

0x0D

R13

W/R

LNAVTH_H[3:0]

LNAVTH_L[3:0]

  

0x0E

R14

W/R

MIXVTH_H[3:0]

MIXVTH_L[3:0]

  

0x0F

R15

W/R

FLT_EXT_WIDEST

ldo5vh

pwd_ldo_5v

CLK_OUT_ENB

1 ring clk=0

CALI_CLK

CLK_AGC_ENB

GPIO_enable

  

0x10

R16

W/R

SEL_DIV[2:0]

REF_DIV2

xtal_drive low=1

agc_clk_s2

CAPX[1:0]

  

0x11

R17

W/R

PW_LDO_A[1:0]

CP_CUR

pwd_divider

1 1 biasHF

  

0x12

R18

W/R

VCO_CURRENT

DIS_DITHER

PW_SDM

cp_offset

Cp_0406

  

0x13

R19

W/R

PLL auto_tune clk 0=on

band force 1=on

VCO band

  

0x14

R20

W/R

S_I2C[1:0]

N_I2C[5:0]

  

0x15

R21

W/R

SDM_IN[8:1]

  

0x16

R22

W/R

SDM_IN[16:9]

  

0x17

R23

W/R

PW_LDO_D[1:0]

DIV_BUF_CURR

OPEN_D

1 0 pw_IQ

0 PWD_IQ

  

0x18

R24

W/R

0 pw_ringout

1 ring_cp

- ring_se23

- ring power=1

N_RING

  

0x19

R25

W/R

PWD_RFFILT

ring_cp_current

POLYFIL_CUR

SW_AGC

1 1 ring_pw

ring_seldiv

  

0x1A

R26

W/R

RFMUX[1:0]

AGC_CLK

PLL_AUTO_CLK[1:0]

RFFILT{1:0]

  

0x1B

R27

W/R

TF_NCH[3:0]

TF_LP[3:0]

  

0x1C

R28

W/R

PDET3_GAIN[3:0] – vga

lna_top_p1

DISHARGE_MODE

mixer src 0=rf 1=ring

VCO_Out

  

0x1D

R29

W/R

1 1 DETECT_BW

PDET1_GAIN[2:0] LNA

PDET2_GAIN[2:0] mixer

  

0x1E

R30

W/R

sw pdect 1=det3

FILTER_EXT

ext_enable_point

PDET_CLK[4:0]

  

0x1F

R31

W/R

LT_ATT

1(pwd_xtal?)

0

0

0

0

ring_att

  

Reg

Address

Reg

Name

Write/

Read

B7

B6

B5

B4

B3

B2

B1

B0

   

0x00

R0

R

1

0

0

1

0

1

1

0

Signature (datasheet)

  

0x01

R1

R

-

-

ADC OUTPUT

ADC on output from PDET3 (and possibly other options?)

  

0x02

R2

R

0 (1) autotune done?

LOCK (1=lock)

VCO_BAND

VCO ind: 00000 – 111111 depending on where in the locking range VCO is working

  

0x03

R3

R

MIXER GAIN

LNA GAIN

gain? output

Check behavior? May be strange without AGC enabled

 

0x04

R4

R

-

-

VCO_FINE_TUNE

CAL_CODE

CAL_CODE: to explore, VCO_FINE_TUNE bogus?